There are many different D flip-flop IC’s available in both TTL and CMOS packages with the more common being the 74LS74 which is a Dual D flip-flop IC, which contains two individual D type bistable’s within a single chip enabling single or master-slave toggle flip-flops to be made. “Master-Slave D-type flip flops” can be constructed by the cascading together of two latches with opposite clock phases as shown. Then the output stage appears to be triggered on the negative edge of the clock pulse. On the trailing edge of the clock signal (HIGH-to-LOW) the second “slave” stage is now activated, latching on to the output from the first master circuit. On the leading edge of the clock signal (LOW-to-HIGH) the first stage, the “master” latches the input condition at D, while the output stage is deactivated. The basic D-type flip flop can be improved further by adding a second SR flip-flop to its output that is activated on the complementary clock signal to produce a “Master-Slave D-type flip flop”. Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are edge triggered The Master-Slave D Flip Flop In other words the output is “latched” at either logic “0” or logic “1”. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both held at logic level “1” so it will not change state and store whatever data was present on its output before the clock transition occurred. The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the clock input is HIGH. This then forms the basis of another sequential device called a D Flip Flop. The effect is that D input condition is only copied to the output Q when the clock input is active. To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data input from the flip flop’s latching circuitry after the desired data has been stored. By adding an inverter (NOT gate) between the Set and Reset inputs, the S and R inputs become complements of each other ensuring that the two inputs S and R are never equal (0 or 1) to each other at the same time allowing us to control the toggle action of the flip-flop using one single D (Data) input. The D Flip Flop is by far the most important of all the clocked flip-flops. This state will force both outputs to be at logic “1”, over-riding the feedback latching action and whichever input goes to logic level “1” first will lose control, while the other input still at logic “0” controls the resulting state of the latch.īut in order to prevent this from happening an inverter can be connected between the “SET” and the “RESET” inputs to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally called. The D-type Flip-flop overcomes one of the main disadvantages of the basic SR NAND Gate Bistable circuit in that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden.
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